RISC-V processors: Fast core SiFive P650 and 15 new specifications


According to developer SiFive, the Performance P650 is the most powerful processor core to date with the RISC-V instruction set architecture. In one to two years, it could be used in Linux-compatible processors with up to 16 processor cores, 16MB L3 cache, and many memory channels. Each core has a 64KB L1 cache (32 each for data and commands) and a 256KB L2 cache. Computing power per cycle is expected to be comparable to that of the ARM Cortex-A77 announced in 2019.

Areas of application of SoCs with Core P650 SiFive sees in servers, vehicles and mobile devices, among others. The SiFive Performance P650 meets the RISC-V RV64GCB specification as well as the new specifications for hypervisor and virtualization approved by the RISC-V Foundation.

A few days before the RISC-V summit in San Francisco, members of the RISC-V Foundation ratified 15 specifications that describe a total of 40 extensions to the RISC-V-ISA. As mentioned, this includes virtualization functions, but also vector commands and scalar cryptography commands. Current versions of RISC-V specifications can be found on GitHub.

Like SiFive, it is also located in Silicon Valley, very close to Intel’s headquarters in Santa Clara. The always fashionable Rivos company save. Some top CPU experts who have worked for companies like PA Semi are probably working on a RISC-V server chip there. Rivos is already a member of the RISC-V-Foundation and has obtained the PCI-ID 7933 (0x1EFD).

In other places, the startup problems of RISC-V technology become visible. So need the RISC-V-SoC Special StarFive JH7100 Linux Patches for DMA Access from I / O Controllersbecause the chip does not itself take care of the consistency of the cache. Similar Restrictions apply to Allwinner D1 with RV64GC XuanTie C906 core.

  • Podcast bit noise on the topic of RISC-V:

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